1. Field of the Invention
The present invention relates to a logic simulation machine for carrying out a test program for a logic device and, more particularly, to a gate addressing system of a logic simulation machine for, at high speed, generating circuit data for simulation by reading at a high speed circuit model data for the logic simulation machine from a data base on a module-by-module basis and generating intermodule connection data.
Recent logic devices use many VLSIs. Thus, a single design deficiency in a logic device will greatly delay its development and increase its development cost. Therefore, the design of a logic device must be fully verified before it is manufactured. To this end, a designer uses a logic simulator to carry out a test program and the correctness of his design is confirmed when a comparison between results of the simulation and expected values indicates equality. However, recent devices may have several millions of gates and a clock rate as high as 1 GHz. It has been reported that the execution of the test program, which operates on an actual unit for only one minute, using a simulator as software on a large computer requires a period as long as 190 years. This is one billion times slower than the actual unit.
For this reason, a logic simulation machine was invented which is about 10,000 times faster than the conventional simulator described above. With this machine, the test program can be executed in about one week, thus considerably decreasing the verification time after a logic design has been completed to some extent.
To carry out the test program by the logic simulation machine, it is required to convert a data base for design to a circuit data base for a machine.
Heretofore, circuit data for a machine has been expanded to a flat (not hierarchical) form of element levels. The data is represented by types of elements and connection relationships among elements. The elements are generally gates and the types of elements represent AND, NOR, etc. The connection relationship represents, as a minimum, an element (and its input pin) connected to the output pin of a certain element. The connection relationship is represented by numbers which are uniquely assigned to elements and pins.
For example, the connection relationship in a circuit such as that shown in FIG. 29 is conventionally given as follows. First, unique numbers are assigned to gates, as shown in FIG. 30. The input pins of gates are consecutively numbered, starting with 0, from the top.
The connection relationships form a table which provides information on to which gates and to what numbered pin of these gates the output of a certain other gate is to be connected. For example, the output of the tenth gate is connected to the second pin of the thirteenth gate and the second pin of the sixteenth gate. The method of storing this information in the table will be explained with reference to FIGS. 31 through 34. In FIGS. 31 through 34, the first column ADR represents row numbers (addresses) of the table. Thus, the ADR does not represent information to be written into the table. The second column to the fifth column represent the actual contents of the table. The second column END indicates the end of the list of connection information (the list ends at 1). The third column PTR represents whether data in each row represents an actual gate number (PTR=0) or a pointer to the list in which gate numbers are written (PTR=1). The fourth column GATE represents a gate number when PTR=0 and points to a row number (or address) (address ADR) in the same table when PTR=1. The fifth column INO represents an input pin number when PTR=0 and has no meaning when PTR=1. To determine to which gate and to which of its inputs (plus) the output of the tenth gate is connected, the address 10 of the table is referred to. The address 10 indicates PTR=1 and points to the list starting with address 110. The list starting with the address 110 has two rows. This can be seen from that END=1 in address 111. Since PTR=0, gate numbers are written in these two rows. Thus, it will be appreciated that the output of the gate 10 is connected to the pin 2 of the gate 13 and the pin 2 of the gate 16. These gates, connected to the output pin of the gate 10, are called fanout gates. In general, it is said that the average number of fanout gates for one gate is three.
FIG. 35 is a block diagram of hardware for reading numbers of fanout gates from the conventional table with a data structure described in conjunction with FIGS. 31 through 34. This hardware comprises a memory (FAN) 1 for storing the data END, PTR, GATE and INO described in conjunction with FIGS. 31 to 34, an address register (FADR) 2 for designating an address for reading a fanout gate number from the memory 1, a multiplexer 3 and an OR circuit.
When the data END or PTR in the memory 1 is 1, the output of the OR circuit 4 is 1, in which case data from the multiplexer 3 is loaded into the address register 2. When either the END or PTR are both 0 and the output of OR circuit 4 is 0, however, the contents of the address register 2 are advanced. When PTR=1, the GATE in the memory 1 indicates a pointer value which is stored in the address register 2 via the multiplexer 3. When PTR=0 and END=1, the externally applied next gate number is entered into the address register 2 via the multiplexer 3. When END=1, a next signal is applied to the outside, which makes effective the externally applied next-gate number signal. This hardware is also used as the basis of an embodiment of the present invention and thus its operation will be described in detail below.
With the conventional compile method, it is necessary to assign up to one million unique gate numbers to gates when the number of the gates is one million, and to represent connection relationships among about three million fan-out gates of the one million gates using those gate numbers. This process is called compilation. For compilation of one million gates a CPU time as long as several hours is needed, even with a large computer. Although the ratio of the CPU time of a large computer to the actual processing time depends on the number of jobs which run in parallel, the actual processing time is three or more times slower. Thus, the compilation will need substantially a full day.
If the run time of the logic simulation machine is one week, the compile time is not a serious problem. When an error (disagreement between the result at a checkpoint of simulation and the expected value) is detected in the simulation machine, the continuation of the simulation is meaningless so long as a design deficiency that causes the error is not removed. The occurrence of many errors is inevitable in the initial stage of design in particular. Thus, the compile time becomes predominant, in which case the logic simulation machine cannot fully show its power.
The technical problems with the conventional data structure or gate addressing method are summarized as follows.
The first problem is that gates need to be reassigned unique consecutive numbers.
A logic device is generally designed hierarchically. Various units in the hierarchy include a level of an LSI or printed circuit board and a level of a logical block within an LSI. Circuit data is usually compiled in units of the hierarchy. To generate circuit data of the entire logic device, however, the gates must be reassigned unique consecutive numbers.
The second problem is that, even if the same partial circuit is used in plural locations, this fact is not utilized.
Actually, the circuit of FIG. 30 makes repeated use of a partial circuit (macro) of the same structure. A circuit comprising gates numbered 10 to 17 and input pins numbered 1 to 3 corresponds to this macro. Besides this macro, there are four identical macros in the circuit diagram (for example, a circuit comprised of gates 20 to 27 and input pins 4, 5 and 6 and a circuit comprised of gates 40 to 47 and input pins thereto which are shown unnumbered and connected to the output pins of the gates 60, 61 and 62). Such information is not utilized.
The third problem is that, with the data structure of the conventional table described in conjunction with FIGS. 31 to 34, addresses corresponding in number to (1+F).times.the number of gates are required, F representing the average number (about three) of fan-outs of a gate. This increases the size of the table. For example, in FIGS. 31 to 34, data of ADR=1 is the pointer to the starting address 101 of the list of fan-out gates. By referring to the list in the addresses 101 to 103 it becomes possible to know the fan-outs of the gate numbered 1. That is, there are four (i.e. H3) table addresses for the gate numbered 1.
The fourth problem, which is similar to the second problem, is that the connection information on a certain partial circuit cannot be expanded on a memory to make repeated use of it for other partial circuits of the same structure.
The fifth problem is that, even if the entire circuit is composed of several modules, since a simulation model of each module is expanded once to the level of gates to generate the simulation model, the simulation model of a previously generated module cannot be used as it is and the recompilation of the entire circuit is needed even when some modules are subjected to modification.